(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to the chemical-mechanical-planarization of semiconductor wafers.
(2) Background of the Invention and Description of Previous Art
The fabrication of integrated circuits not only involves the forming of semiconductor devices within the surface of a semiconductor wafer but also the creation of a complex network of wiring interconnections which comprise the electrical circuitry of the completed chip. These interconnections are accomplished by the alternate deposition of thin layers of conductive and insulating materials over the semiconductor devices. Each conductive layer is patterned by photolithographic techniques to form the wiring design for that level. This patterning process produces a surface with topological features, which, if no steps were taken, would replicate itself in each succeeding layer.
Conductive layers, usually metals such as aluminum or copper, are deposited by physical-vapor-deposition (PVD) techniques such as vacuum evaporation or sputtering. These methods do not provide conformal coverage and the presence of topological features on the surface onto which they are deposited result in non-uniformities in thickness and other problems related to the shadowing effects of non-planar surfaces.
Frequently two to four levels of interconnection metallurgy are required to form the required circuits. In order to provide a planar surface for each level of metal, various methods have been used to planarize the insulator surface. Glasses which flow when heated are commonly used to accommodate the first layer of metallization. Subsequent levels where elevated temperatures are no longer permissible, employ layers of materials which are deposited as liquids and then cured to form solid layers. Such layers of spin-on-glasses and organic polymers provide an improved local surface planarity. Subsequent reactive-ion-etching(RIE) removes the polymers and translates the new surface to the insulating layer.
Although these methods can provide to local planarization, they are impractical for the large wafers used present day technology because they cannot provide planarization over a large area. This is because the integrated circuit chips themselves contain discrete regions of different topological complexity such as memory arrays located within regions of logic circuits.
Recent years have seen an increased interest in the old technique which is used to provide the wafer with a planar surface in the first place—chemical-mechanical-polishing(CMP). At first thought, CMP is a seemingly crude method for dealing with dimensions of the order of hundredths of a micron. However, because of it's uniquely global planarizational ability, the CMP technique has been diligently and painstakingly refined and perfected for in-process planarization over the past decade. The main thrust of this effort has been dedicated to the development of highly sophisticated polishing machines. As a result, the CMP technique is now widely used for global planarization of in-process semiconductor wafers in the fabrication of integrated circuits.
Modern, high precision CMP machines are described, for example, by Hempel, U.S. Pat. No. 5,597,346, Kim, U.S. Pat. No. 5,695,392, Zuniga, et. al. U.S. Pat. Nos. 6,132,298 and 6,361,420 B1, Yi, U.S. Pat. No. 6,146,260, and Lin, et. al., U.S. Pat. No. 6,183,350 B1.
An example of a simple CMP polishing machine as described by Lai, et. al., U.S. Pat. No. 6,224,472 B1 is shown in FIG. 1a includes a head 10 which holds a wafer 12 to be polished on its under side, usually by vacuum applied to the back of the wafer 12 through numerous ports 14. The head 10 rotates and presses the wafer 12 against a polishing pad 16 mounted on an upright rotating pedestal or platen 18. A polishing slurry 20 is fed to the pad surface during operation. The underside of the head 10 is fitted with a retaining ring 22 which surrounds the wafer 12. FIG. 1b illustrates a typical retaining ring 22. The retaining ring 22 not only keeps the wafer 12 confined to the underside of the head 10 but also includes multiple channels 24 through which a polishing slurry 24 is introduced to the wafer/pad interface.
The polishing rate at wafer edge is usually different from that on the rest of the wafer. In addition, the polishing rate profile at the wafer edge does not vary much with different process parameters or materials being polished. Typically, the polishing rate at less than 5 mm. from the wafer edge is always lower than that at the wafer center. This puts a limitation on the thickness uniformity especially at the wafer edge that can be achieved by CMP and hence makes the wafer edge region unsuitable for use in integrated circuits, and decreases the yield.
It would be desirable to be able, by polishing parameter adjustments, to regulate the polishing rate in the edge region of the wafer so as to achieve a uniform polish rate over the entire wafer and thereby extend the overall usable area of the wafer. It would be further desirable to be able, by polishing parameter adjustments, to adjust the polishing rate in the edge region of the wafer so as to polish the wafer edge region at a significantly higher or a significantly lower rate than that over the main portion of the wafer. With this capability, either surface planarity and/or surface layer thickness uniformity can be extended further out into the edge region.
Zuniga, et. al., '298 and '420, describe a polishing head structure which provides adjustable pressure during polishing to the wafer in order to cause even polishing. A first pressure is applied to a center portion of the wafer through a membrane and a second pressure is applied to a perimeter portion of the wafer through an edge load ring which is more rigid than the membrane. In Zuniga, et. al., U.S. Pat. No. 6,436,228 B1, there are shown a wafer substrate retaining ring which provides a plurality of discrete points of contact between the ring and the wafer. However, these various designs do not address the delivery of slurry under the wafer.
Notable progress has been made in retaining ring design, primarily with regards to the uniform and controllable flow of slurry past the retaining ring to the underside of the wafer. Chiu, et. al., U.S. Pat. No. 5,944,593 shows a retaining ring which features a plurality of straight channels for the delivery of a slurry and an added circular groove which provides an internal interconnection of all the straight channels. This design provides a buffering effect to the delivery of slurry. Lin, et. al., U.S. Pat. No. 6,062,963 cites the use of slurry delivery channels which are tapered to even out the slurry flow at the edge of the wafer. Glashauser, U.S. Pat. No. 6,419,567 B1 also provides an improved slurry delivery system through the retaining ring with a central circular channel in the base of the retaining ring which is fed with slurry through two inlets and which distributes slurry to the wafer through a plurality of inner channels. Pham, et. al., U.S. Pat. No. 6,447,380 B1 like Glashauser, also addresses modifications of the retaining ring to improve slurry delivery to the wafer.
While most of the retaining ring design effort has directed at slurry delivery, little has been given towards edge control. The Mirra-Mesa™ polisher manufactured by Applied Materials Corporation of Palo Alto, Calif. permits the application of a first pressure to the backside of the wafer during polishing through a flexible membrane (designated as membrane pressure or MP). A second pressure, designated as retaining ring pressure (RRP), is applied to a retaining ring which surrounds and confines the wafer. A third pressure, referred to as inner tube pressure (ITP), permits the application of an additional controllable downward pressure to a circular region near the edge of the wafer by means of an inflatable tube, between the membrane and the wafer. With this capability, the present inventors have found that, using the conventional retaining ring shown if FIG. 1b, for several values of inner tube pressures (ITP) at a fixed retaining ring pressure (RRP) the polishing rate always dropped off within the outermost 5 mm. edge portion of a 200 mm. wafer.
In response, the present inventors have developed a new retaining ring design which permits edge polishing rates which can be made significantly greater or significantly less than the mean overall wafer polishing rate depending on the choice of ITP and RRP. None of the prior art provides the capability of such wafer edge polishing rate adjustment by a simple in-situ pressure change. In view of the above the improved retaining ring structure cited by the present invention helps to minimize deformation of the polishing pad and thereby is capable of providing good thickness uniformity and/or surface planarity over a greater portion of the wafer than was previously possible.